Update packages

sources_non_forked/vim-snippets/snippets/systemverilog.snippets

@@ -1,37 +1,6 @@
-# if statement
-snippet if
-	if (${1}) begin
-		${0}
-	end
-# If/else statements
-snippet ife
-	if (${1}) begin
-		${2}
-	end
-	else begin
-		${1}
-	end
-# Else if statement
-snippet eif
-	else if (${1}) begin
-		${0}
-	end
-#Else statement
-snippet el
-	else begin
-		${0}
-	end
-# While statement
-snippet wh
-	while (${1}) begin
-		${0}
-	end
-# Repeat Loop
-snippet rep
-	repeat (${1}) begin
-		${0}
-	end
-# Foreach Loopo
+extends verilog
+
+# Foreach Loop
 snippet fe
 	foreach (${1}) begin
 		${0}
@@ -41,24 +10,6 @@ snippet dowh
 	do begin
 		${0}
 	end while (${1});
-# Case statement
-snippet case
-	case (${1})
-		{$2}: begin
-			${0}
-		end
-		default: begin
-		end
-	endcase
-# CaseZ statement
-snippet casez
-casez (${1})
-		{$2}: begin
-			${0}
-		end
-		default: begin
-		end
-	endcase
 # Combinational always block
 snippet alc
 	always_comb begin ${1:: statement_label}
@@ -74,11 +25,6 @@ snippet all
 	always_latch begin ${1:: statement_label}
 		${0}
 	end $1
-# Module block
-snippet mod
-	module ${1:module_name} (${2});
-		${0}
-	endmodule : $1
 # Class
 snippet cl
 	class ${1:class_name};