mirror of
https://github.com/amix/vimrc
synced 2025-07-09 02:25:00 +08:00
Use sources_non_forked folder for pathogen path, with sources_non_forked_fallback folder as fallback.
This commit is contained in:
Wu Tingfeng
@ -1,5 +0,0 @@
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" Author: suoto <andre820@gmail.com>
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" Description: Adds support for HDL Code Checker, which wraps vcom/vlog, ghdl
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" or xvhdl. More info on https://github.com/suoto/hdl_checker
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call ale#handlers#hdl_checker#DefineLinter('verilog')
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@ -1,43 +0,0 @@
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" Author: Masahiro H https://github.com/mshr-h
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" Description: iverilog for verilog files
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call ale#Set('verilog_iverilog_options', '')
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function! ale_linters#verilog#iverilog#GetCommand(buffer) abort
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return 'iverilog -t null -Wall '
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\ . ale#Var(a:buffer, 'verilog_iverilog_options')
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\ . ' %t'
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endfunction
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function! ale_linters#verilog#iverilog#Handle(buffer, lines) abort
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" Look for lines like the following.
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"
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" tb_me_top.v:37: warning: Instantiating module me_top with dangling input port 1 (rst_n) floating.
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" tb_me_top.v:17: syntax error
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" memory_single_port.v:2: syntax error
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" tb_me_top.v:17: error: Invalid module instantiation
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let l:pattern = '^[^:]\+:\(\d\+\): \(warning\|error\|syntax error\)\(: \(.\+\)\)\?'
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let l:output = []
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for l:match in ale#util#GetMatches(a:lines, l:pattern)
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let l:line = l:match[1] + 0
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let l:type = l:match[2] =~# 'error' ? 'E' : 'W'
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let l:text = l:match[2] is# 'syntax error' ? 'syntax error' : l:match[4]
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call add(l:output, {
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\ 'lnum': l:line,
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\ 'text': l:text,
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\ 'type': l:type,
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\})
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endfor
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return l:output
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endfunction
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call ale#linter#Define('verilog', {
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\ 'name': 'iverilog',
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\ 'output_stream': 'stderr',
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\ 'executable': 'iverilog',
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\ 'command': function('ale_linters#verilog#iverilog#GetCommand'),
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\ 'callback': 'ale_linters#verilog#iverilog#Handle',
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\})
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@ -1,60 +0,0 @@
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" Author: Masahiro H https://github.com/mshr-h
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" Description: verilator for verilog files
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" Set this option to change Verilator lint options
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if !exists('g:ale_verilog_verilator_options')
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let g:ale_verilog_verilator_options = ''
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endif
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function! ale_linters#verilog#verilator#GetCommand(buffer) abort
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" the path to the current file is systematically added to the search path
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return 'verilator --lint-only -Wall -Wno-DECLFILENAME '
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\ . '-I%s:h '
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\ . ale#Var(a:buffer, 'verilog_verilator_options') .' '
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\ . '%t'
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endfunction
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function! ale_linters#verilog#verilator#Handle(buffer, lines) abort
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" Look for lines like the following.
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"
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" %Error: addr_gen.v:3: syntax error, unexpected IDENTIFIER
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" %Warning-WIDTH: addr_gen.v:26: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS's CONST '20'h0' generates 20 bits.
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" %Warning-UNUSED: test.v:3: Signal is not used: a
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" %Warning-UNDRIVEN: test.v:3: Signal is not driven: clk
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" %Warning-UNUSED: test.v:4: Signal is not used: dout
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" %Warning-BLKSEQ: test.v:10: Blocking assignments (=) in sequential (flop or latch) block; suggest delayed assignments (<=).
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" Since version 4.032 (04/2020) verilator linter messages also contain the column number,
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" and look like:
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" %Error: /tmp/test.sv:3:1: syntax error, unexpected endmodule, expecting ';'
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"
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" to stay compatible with old versions of the tool, the column number is
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" optional in the researched pattern
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let l:pattern = '^%\(Warning\|Error\)[^:]*:\s*\([^:]\+\):\(\d\+\):\(\d\+\)\?:\? \(.\+\)$'
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let l:output = []
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for l:match in ale#util#GetMatches(a:lines, l:pattern)
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let l:item = {
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\ 'lnum': str2nr(l:match[3]),
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\ 'text': l:match[5],
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\ 'type': l:match[1] is# 'Error' ? 'E' : 'W',
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\ 'filename': l:match[2],
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\}
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if !empty(l:match[4])
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let l:item.col = str2nr(l:match[4])
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endif
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call add(l:output, l:item)
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endfor
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return l:output
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endfunction
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call ale#linter#Define('verilog', {
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\ 'name': 'verilator',
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\ 'output_stream': 'stderr',
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\ 'executable': 'verilator',
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\ 'command': function('ale_linters#verilog#verilator#GetCommand'),
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\ 'callback': 'ale_linters#verilog#verilator#Handle',
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\ 'read_buffer': 0,
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\})
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@ -1,52 +0,0 @@
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" Author: John Gentile <johncgentile17@gmail.com>
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" Description: Adds support for Mentor Graphics Questa/ModelSim `vlog` Verilog compiler/checker
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call ale#Set('verilog_vlog_executable', 'vlog')
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" See `$ vlog -h` for more options
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call ale#Set('verilog_vlog_options', '-quiet -lint')
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function! ale_linters#verilog#vlog#GetCommand(buffer) abort
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return '%e ' . ale#Pad(ale#Var(a:buffer, 'verilog_vlog_options')) . ' %t'
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endfunction
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function! ale_linters#verilog#vlog#Handle(buffer, lines) abort
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"Matches patterns like the following:
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"** Warning: add.v(7): (vlog-2623) Undefined variable: C.
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"** Error: file.v(1): (vlog-13294) Identifier must be declared with a port mode: C.
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let l:pattern = '^**\s\(\w*\): \([a-zA-Z0-9\-\.\_\/ ]\+\)(\(\d\+\)):\s\+\(.*\)'
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let l:output = []
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for l:match in ale#util#GetMatches(a:lines, l:pattern)
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call add(l:output, {
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\ 'lnum': l:match[3] + 0,
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\ 'type': l:match[1] is? 'Error' ? 'E' : 'W',
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\ 'text': l:match[4],
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\ 'filename': l:match[2],
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\})
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endfor
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"Matches patterns like the following:
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"** Warning: (vlog-2623) add.v(7): Undefined variable: C.
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"** Error: (vlog-13294) file.v(1): Identifier must be declared with a port mode: C.
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" let l:pattern = '^**\s\(\w*\):[a-zA-Z0-9\-\.\_\/ ]\+(\(\d\+\)):\s\+\(.*\)'
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let l:pattern = '^**\s\(\w*\):\s\([^)]*)\) \([a-zA-Z0-9\-\.\_\/ ]\+\)(\(\d\+\)):\s\+\(.*\)'
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for l:match in ale#util#GetMatches(a:lines, l:pattern)
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call add(l:output, {
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\ 'lnum': l:match[4] + 0,
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\ 'type': l:match[1] is? 'Error' ? 'E' : 'W',
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\ 'text': l:match[2] . ' ' . l:match[5],
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\ 'filename': l:match[3],
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\})
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endfor
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return l:output
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endfunction
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call ale#linter#Define('verilog', {
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\ 'name': 'vlog',
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\ 'output_stream': 'stdout',
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\ 'executable': {b -> ale#Var(b, 'verilog_vlog_executable')},
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\ 'command': function('ale_linters#verilog#vlog#GetCommand'),
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\ 'callback': 'ale_linters#verilog#vlog#Handle',
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\})
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@ -1,35 +0,0 @@
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" Author: John Gentile <johncgentile17@gmail.com>
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" Description: Adds support for Xilinx Vivado `xvlog` Verilog compiler/checker
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call ale#Set('verilog_xvlog_executable', 'xvlog')
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call ale#Set('verilog_xvlog_options', '')
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function! ale_linters#verilog#xvlog#GetCommand(buffer) abort
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return '%e ' . ale#Pad(ale#Var(a:buffer, 'verilog_xvlog_options')) . ' %t'
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endfunction
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function! ale_linters#verilog#xvlog#Handle(buffer, lines) abort
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"Matches patterns like the following:
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" ERROR: [VRFC 10-1412] syntax error near output [/path/to/file.v:5]
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let l:pattern = '^ERROR:\s\+\(\[.*\)\[.*:\([0-9]\+\)\]'
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let l:output = []
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" NOTE: `xvlog` only prints 'INFO' and 'ERROR' messages
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for l:match in ale#util#GetMatches(a:lines, l:pattern)
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call add(l:output, {
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\ 'lnum': l:match[2] + 0,
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\ 'type': 'E',
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\ 'text': l:match[1],
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\})
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endfor
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return l:output
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endfunction
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call ale#linter#Define('verilog', {
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\ 'name': 'xvlog',
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\ 'output_stream': 'stdout',
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\ 'executable': {b -> ale#Var(b, 'verilog_xvlog_executable')},
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\ 'command': function('ale_linters#verilog#xvlog#GetCommand'),
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\ 'callback': 'ale_linters#verilog#xvlog#Handle',
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\})
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@ -1,42 +0,0 @@
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" Author: Nathan Sharp <nwsharp+eda@live.com>
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" Description: Yosys for Verilog files
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call ale#Set('verilog_yosys_executable', 'yosys')
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call ale#Set('verilog_yosys_options', '-Q -T -p ''read_verilog %s''')
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function! ale_linters#verilog#yosys#GetCommand(buffer) abort
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return '%e ' . ale#Var(a:buffer, 'verilog_yosys_options') . ' 2>&1'
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endfunction
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function! ale_linters#verilog#yosys#Handle(buffer, lines) abort
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let l:output = []
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let l:path = fnamemodify(bufname(a:buffer), ':p')
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for l:match in ale#util#GetMatches(a:lines, '^\([^:]\+\):\(\d\+\): \(WARNING\|ERROR\): \(.\+\)$')
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call add(l:output, {
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\ 'lnum': str2nr(l:match[2]),
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\ 'text': l:match[4],
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\ 'type': l:match[3][0],
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\ 'filename': l:match[1],
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\})
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endfor
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for l:match in ale#util#GetMatches(a:lines, '^\(Warning\|ERROR\): \(.\+\)$')
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call add(l:output, {
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\ 'lnum': 1,
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\ 'text': l:match[2],
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\ 'type': l:match[1][0],
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\})
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endfor
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return l:output
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endfunction
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call ale#linter#Define('verilog', {
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\ 'name': 'yosys',
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\ 'output_stream': 'stdout',
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\ 'executable': {b -> ale#Var(b, 'verilog_yosys_executable')},
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\ 'command': function('ale_linters#verilog#yosys#GetCommand'),
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\ 'callback': 'ale_linters#verilog#yosys#Handle',
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\ 'lint_file': 1,
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\})
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